1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device and, more particularly, to a method of fabricating an exposure mask for semiconductor manufacture to improve the accuracy of pattern-critical dimensions of the exposure mask.
2. Description of the Related Art
As is well known, in a semiconductor manufacturing process, contact holes and other patterns are generally formed in accordance with photolithography processes. The photolithography process comprises a process for coating photo sensitive polymer (hereinafter, referred to as photo resist) on a layer to be etched, a process for selectively exposing the coated photo resist by using a predetermined exposure mask, and a process for development to form a photo resist pattern in a predetermined shape by removing the exposed or unexposed part of the photo resist using a predetermined chemical solution.
As mentioned above, exposure of the photo resist is accomplished by using an exposure mask. The exposure mask generally has a structure such that an opaque chrome pattern is formed on a transparent quartz substrate.
According to a conventional method for manufacturing the exposure mask, the opaque chrome layer and the photo resist sensitizing to E-beam are sequentially formed on the quartz substrate and then an E-beam is irradiated on the photo resist. Subsequently, development and etching processes are performed in sequence.
However, as shown in FIG. 1, the conventional method has a problem in that during the exposure process on a photo resist 3 using E-beam 20, charge-up 4 of the exposure area is not completely controlled, resulting in failure to obtain a mask pattern of desirable critical dimension. In FIG. 1, the photoresist 3 is shown overlying a chrome layer 2 on a quartz substrate 1.
According to the conventional method, in order to prevent charge-up during the E-beam exposure, layout of the chrome layer 2 for shielding light is controlled to prevent burst of the mask pattern. However, in consideration of the layout of a circuit pattern realized on a wafer, the above-mentioned method has a limitation in controlling the layout of the chrome layer and therefore, it is difficult to prevent charge-up, especially local charge-up.
As a result, it is difficult to achieve the critical dimension accuracy of a mask pattern required for fabricating an exposure mask for manufacture of a highly-integrated circuit over 256 M and therefore, it is practically difficult to realize an exposure mask for a highly-integrated circuit.
Therefore, the present invention has been made to solve the above problems and an object of the present invention is to provide a method of fabricating exposure mask for semiconductor manufacture to improve the critical dimension accuracy of mask patterns.
Another object of the present invention is to improve the critical dimension accuracy of a mask pattern, thereby providing a method of fabricating an exposure mask for semiconductor manufacture capable of producing an exposure mask for highly-integrated circuit manufacture and highly-integrated circuits.
In order to accomplish the above objects, the present invention is directed to a method comprising the steps of forming a chrome layer, a first photo resist, a conductive layer and a second photo resist on a transparent quartz substrate, in sequence; forming a second photo resist pattern by exposing and developing the second photo resist; forming a conductive layer pattern by etching the conductive layer using the second photo resist pattern as an etch barrier; removing the second photo resist pattern; forming an oxide layer as a layer for shielding light at the surface of the conductive layer pattern by oxidizing the conductive layer pattern; exposing the first photo resist using the conductive layer pattern having the oxide layer at the surface thereof; forming a first photo resist pattern exposing the chrome layer by developing the exposed first photo resist; forming a mask pattern including the chrome layer by selectively etching the exposed chrome layer parts; and removing the conductive layer pattern including the oxide layer and the first photo resist pattern.
In the method of fabricating an exposure mask according to the present invention, an Ag layer is formed as the conductive layer, the second photo resist is exposed by using a high voltage E-beam or focused ion beam as the light source, and the first photo resist is exposed by using G-line, I-line or KrF as the light source.
The objects and features of the invention may be understood with reference to the following detailed description of an illustrative embodiment of the invention, taken together with the accompanying drawings.